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| 商品编号: |
xdvd1661c |
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| 商品名稱： |
電子設計自動化工具 SynaptiCAD Product Suite V16.00a 英文版 CD |
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| 碟片數量： |
1片 |
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| 銷售價格： |
200 |
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| 瀏覽次數： |
23150 |
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【轉載TXT文檔】 |
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| 電子設計自動化工具 SynaptiCAD Product Suite V16.00a 英文版 CD |
SynaptiCAD was founded by electrical engineers to create design tools that helped engineers think critically about their designs. Being engineers themselves, they were frustrated by having to almost complete a design before being able to get simulation results. Our founders decided that there must be a better approach for interacting with design tools and from this simple idea they created SynaptiCAD, a company that creates “tools for the thinking mind”. This idea permeates all of our tool interfaces. With SynaptiCAD's tools you are able to begin analyzing and simulating design ideas right away without having to complete an entire circuit model or schematic. Our tools automatically handle many of the minor details involved in the design effort, leaving you more time to focus on the bigger picture.
Family of products from SynaptiCAD. The software package developed by SynaptiCAD for the analysis of the schemes. Includes 8 programs for finite element analysis of electronic projects: TestBencher Pro, VeriLogger Pro, WaveFormer Pro, WaveFormer Lite, DataSheet Pro, Timing Diagrammer Pro, BugHunter , Gigawave Viewer. In this system synthesis test performs program TestBencher Pro, which generates the HDL-code for the bus synchronous and asynchronous transactions on time charts, drawn up by the user. SynaptiCAD is a multilevel system, as can work together with modeling programs at the levels of RTL, the barrier and the transistor.
Modern integrated CAD VLSI consist of a large number of programs that differ in the orientation of the various design procedures and different types of schemes. The best-known creators of integrated CAD companies are Mentor Graphics, Cadence Design Systems, Synopsys. In addition to these individual programs or group of programs offered by many firms operating in the area of ECAD. One of the known systems of synthesis of tests is SynaptiCAD company Simucad. In this system synthesis test performs program TestBencher Pro, which generates the HDL-code for the bus synchronous and asynchronous transactions on time charts, drawn up by the user. The user can adjust the time diagrams, and TestBencher Pro them quickly studied. Modeling bus transaction is accompanied by fixation of unexpected values of signals and transactions.
Functional Modeling (Functional Simulation) allows you to check the correctness of the scheme. For these purposes, the package Libero is used widely known product ModelSim. In addition, for the generation of test actions used product WaveFormer Lite Company SynaptiCAD. Tracing the project to the selected user FPGA by using its own product Designer, who also has a tool for analyzing the temporal characteristics of Designer's Timer tool, allowing a static analysis of delay of signals on a chip; means placing macros ChipEdit; means the appointment of contacts PinEdit. After placement and routing of the project on a chip using a package of ModelSim executed temporal modeling (timing simulation).
SynaptiCAD 公司出品的EDA（電子設計自動化）工具集合，包括HDL輸入、仿真、測試、波形分析、管腳映射工具等等,是一個很完整的EDA方案。
SynaptiCAD Product Suite 由電機工程師創造設計的一款電子互動設計工具，這個互動概念貫穿於所有的接口。您可以開始分析和模擬設計理念，毋須經完成整個電路模型或示意圖，幫助工程師他們的設計進行批判性的審視。
SynaptiCAD Product Suite 包含了9種功能強大的工具：
1.TestBencher Pro：
用於從獨立於語言的時序邏輯表生成交互式VHDL,Verilog, OpenVera,e, 和TestBuilder 測試基準及總線功能的模型。生成的測試基準能提供基於仿真相應的不同的激發向量，以便於測試基準功能作為一個被測試系統環境的動作模型正常工作。 TestBencher Pro是一個優秀的測試大規模FPGA 和ASIC設計的工具。
2.BugHunter Pro：
一款用於Verilog， VHDL 和C++ 模擬器的圖形調試系統。 BugHunter 支持所有主要的HDL 模擬器，其主要功能包括：單一步驟調試、波形數據串流、項目管理等等。可以偵測程序與幫助系統的交互過程從而發現問題所在。
3.VeriLogger Pro：
Verilog模擬器軟件。提供一個綜合了傳統Verilog模擬器所有特徵的仿真環境，它具有強大的圖形測試矢量產生器。 VeriLogger的快速模型測試使用戶可以對設計中的每個模型進行“自底向上”的測試。
4.WaveFormer Pro：
由時序圖分析器、模擬器和測試向量生成器組合而成。它為設計人員提供了一個集成的環境，可以用來開發數字和模擬線路的時序圖。 WaveFormer Pro可以由Spice模擬器，Mathematica，或Matlab等工具輸入模擬數據。還可以利用WaveFormer Pro 內部擁有的波形函數直接生成模擬信號；或者將從總線上得到的數字信號變換成模擬信號。還可以將模擬信號波形逐段線性地變換成Spice模擬器的電壓信號源。
5.SimuTAG：
一款功能強大和實時地查證出FPGAs 的錯誤的系統。可經由比較FPGA 功能規則反證RTL樣式模擬規則，迅速發現邏輯和綜合錯誤。
6.PinPort：
提供數字硬件與Verilog 或C++的虛擬接口環境。
7.DataSheet Pro：
時間表文件夾管理工具。
8.Timing Diagrammer Pro：
時間表設計工具。
9.Gigawave Viewer：
波形觀測器。
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