Cadence IC6.1.7 ISR22 Virtuoso - 電路仿真設計軟件
CadenceIC是一款專業好用的電路仿真設計軟件，該軟件主要適用於linux系統平台，我們需要使用相應的命令才能完成各類電路的仿真設計操作，擁有輸入原理，造型（Verilog-AMS），電路仿真，自定義模板等，可以用於標準單元設計，RF，混合和模擬信號，也用於存儲器和FPGA設計等操作.

CadenceDesignSystems,Inc.haslaunchedCadenceIC6.1.7ISR22Virtuoso,aformal,streamlinedandautomatedco-designandverificationflowbetweentheCadenceVirtuosoplatformandAllegroandSigritytechnologies.Thishigherlevelofintegrationenablesengineerstodesignconcurrentlyacrossthechip,packageandboard.

Byautomatingwhathasuntilnowbeenamanualprocess,theVirtuosoSystemDesignPlatformminimizeserrorsandcanreducelayoutversusschematic(LVS)timebetweenICandpackagefromdaystominutes.

Untilnow,advancesinsilicontechnologyhavebeensufficientforcontinuedimprovementinmicroelectronicsproducts.Giventhecomplexityoftoday’schips,packagesandboards,ICsbasedonbothsiliconandnon-siliconmaterialsarenowrequiredtodesignoptimalhigh-performancesystems.Asaresult,thistrendisdrivingtheneedforengineerstointegratemultipleheterogeneoustechnologiesinasingleproduct,affectingtheperformanceandfunctionalityofICsandintroducinganewsetofchallengesforsemiconductorcompanies.Toaddressthesechallenges,Cadencehasdevelopedanovel,cross-platformsolutionthatstreamlinesandautomatesthedesignofapackageormodulefeaturingoff-chipdevicesandmultipleICsbasedondifferingprocessdesignkits(PDKs).

TheVirtuosoSystemDesignPlatformallowsICdesignerstoeasilyincludesystem-levellayoutparasiticsintheICverificationflow,enablingtimesavingsbycombiningpackage/boardlayoutconnectivitydatawiththeIClayoutparasiticelectricalmodel.Theresultingautomaticallygenerated“system-aware”schematiccanthenbeeasilyusedtocreateatestbenchforfinalcircuit-levelsimulation.Untilnow,designerswereonlyabletomakechangesaftertime-consumingmanualchecksinvolvingspreadsheetsandotheradhoc/manualmethods,whichcantakedays.Byautomatingthisentireflow,theVirtuosoSystemDesignPlatformeliminatesthehighlymanualanderror-proneprocessofintegratingsystem-levellayoutparasiticmodelsbackintotheICdesigner’sflow,reducingdaysofworktomereminutes.

AboutCadenceVirtuosoSystemDesignPlatform.TheCadenceVirtuosoSystemDesignPlatformlinkstwoworld-classCadencetechnologies—customICdesignandpackage/PCBdesign/analysis—creatingaholisticmethodologythatautomatesandstreamlinesthedesignandverificationflowformulti-dieheterogeneoussystems.

LeveragingtheVirtuosoSchematicEditorandtheVirtuosoAnalogDesignEnvironment,itprovidesasingleplatformforIC-andpackage/system-leveldesigncapture,analysis,andverification.Inaddition,theVirtuosoSystemDesignPlatformprovidesanautomatedbidirectionalinterfacewiththeCadenceSiP-levelimplementationenvironmentandSigrityPowerSI3DEMExtractionOption.

TheVirtuosoSystemDesignPlatformallowsICdesignerstoeasilyincludesystem-levellayoutparasiticsintheICverificationflow,enablingtimesavingsbycombiningpackage/boardlayoutconnectivitydatawiththeIClayoutparasiticelectricalmodel.Theautomaticallygenerated“system-aware”schematicthatresultscanthenbeeasilyusedtocreateatestbenchforfinalcircuit-levelsimulation.TheVirtuosoSystemDesignPlatformautomatesthisentireflow,eliminatingthehighlymanualanderror-proneprocessofintegratingsystem-levellayoutparasiticmodelsbackintotheICdesigner’sflow.

IntegratedHeterogeneousDevices

Manyoftoday’sanalog,RF,andmixed-signaldesignsrequiretheintegrationofmultipleICsacrossvaryingsubstratetechnologiestoachieverequiredperformancegoals.Theintegrationofheterogeneousdevicesallowsdesignerstoachieveresultsthatcan’teasilybeduplicatedusingamonolithicIC(SoC)designapproach.Atthesametime,heterogeneousintegrationintroducesawholenewsetofchallengesfortoday’sdesigners.

Systeminapackage(SiP)isoneofthemostcommonmethodsofintegratingmixedtechnologiesintoasingledesign.ThisapproachrequiresseamlessintegrationbetweentheICandpackagesubstratedesignteamsandanintegratedtoolflow.TheVirtuosoSystemDesignPlatformaddressesthesechallengeswithanovel,cross-platformsolutionthatstreamlinesandautomatesthedesignofapackage/modulefeaturingoff-chipdevicesandmultipleICsbasedondifferingprocessdesignkits(PDKs).

StandaloneSoftwareShippedwithIC6.1.7:

-VirtuosoPowerSystemL(IC6.1.7)
-Voltus-FiCustomPowerIntegritySolutionXLIC6.1.7
-DraculaDesignRuleChecker(4.9)
-DraculaLayoutVs.SchematicVerifier(4.9)
-DraculaParasiticExtractor(4.9)
-DraculaPhysicalVerificationSuite(4.9)
-DraculaPhysicalVerificationandExtractionSuite(4.9)
-VirtuosoChipAssemblyRouter(11.3)

CadenceProductReleasesCompatiblewithIC6.1.7

SpectreCircuitSimulators…………………………(SPECTRE17.10.307)
Pegasus/PhysicalVerificationSystem………………..(PEGASUS18.20.000)
AssuraPhysicalVerification……………………….(ASSURA04.15.115)
XCELIUM………………………………………….(XCELIUMMAIN18.03.008)
Conformal………………………………………..(CONFRML18.10.100)
Innovus………………………………………….(INNOVUS18.10.000)
ManufacturabilityandVariabilitySign-off………….(MVS17.23.000)
ExtractionTools(QRC/QuantusQRC)………………….(EXT18.11.000)
AllegroSigrity…………………………………..(SIG17.00.010)
Silicon-Package-BoardCo-Design…………………….(SPB17.20.043)

WatchanRFdemoshowingtheextractionofaninductorfromlayoutandtheimpactoncircuitsimulationofaVCO.TheCadenceVirtuosoRFSolutionimprovesdesigncycleproductivity,reducingerrorsinmanufacturingandaccountingfortheelectricalandphysicaleffectswithinasingleenvironmentacrossIC,package,andboarddesign.ItsbidirectionalinterfaceintegrateswiththeCadenceSiP-levelimplementationenvironment,SigrityPowerSI3DEMExtractionOptionfiniteelementengine,andNIAWRDesignEnvironmentplatform’sAXIEM3DplanarEMsoftwaretoautomatehoursofmanualworkinRFICandRFModuledesigns.

AboutCadence.Cadenceenableselectronicsystemsandsemiconductorcompaniestocreatetheinnovativeendproductsthataretransformingthewaypeoplelive,workandplay.Cadencesoftware,hardwareandsemiconductorIPareusedbycustomerstodeliverproductstomarketfaster.Thecompany’sSystemDesignEnablementstrategyhelpscustomersdevelopdifferentiatedproducts—fromchipstoboardstosystems—inmobile,consumer,clouddatacenter,automotive,aerospace,IoT,industrialandothermarketsegments.CadenceislistedasoneofFortuneMagazine's100BestCompaniestoWorkFor.

Product:CadenceVirtuosoSystemDesignPlatform
Version:IC6.1.7ISR22*
SupportedArchitectures:x86
WebsiteHomePage:http://www.cadence.com
Language:english
SystemRequirements:Linux
SupportedOperatingSystems:RHEL5,RHEL6,SLES11.0

*TheIC6.1.7ISRstreamisacumulativestreamofallhotfixesthataresubmittedafterthebaserelease.